1. Field of the Invention
The present invention relates generally to USB devices, and more specifically to ULPI physical devices which support the USB 2.0 Link Power Management Addendum.
2. Description of the Related Art
The Universal Serial Bus (USB) was developed to offer PC users an enhanced and easy-to-use interface for connecting an incredibly diverse range of peripherals to their computers. The development of the USB was initially driven by considerations for laptop computers, which greatly benefit from a small profile peripheral connector. Among the many benefits of the USB is a reduction in the proliferation of cables that can affect even the smallest computer installations. In general, USB has become the interface of choice for PCs because it offers users simple connectivity. USB eliminates the need to have different connectors for printers, keyboards, mice, and other peripherals, and supports a wide variety of data types, from slow mouse inputs to digitized audio and compressed video. In addition, USB devices are hot pluggable, i.e. they can be connected to or disconnected from a PC without requiring the PC to be powered off.
The USB specification has seen various revisions, with the USB 2.0 standard challenging the IEEE 1394 interface (“Firewire”) as the interface of choice for high-speed digital video, among others. With the proliferating design of increasingly smarter, faster, and smaller peripherals, the On-The-Go (OTG) Supplement to the USB 2.0 Specification was developed to address the growing popularity of the portable electronic devices market. Some of the advantages of the USB and OTG include the built-in support in form of more than 1.4 billion USB enabled PCs and peripherals shipped worldwide, smooth and trouble-free experience for the user through a compliance and logo program operated by the USB-IF, a wide variety of USB solutions such as intellectual property (IP) blocks, system-on-chip (SOC) parts, discrete chips, software drivers and systems offered by a large group of industry vendors, and design flexibility based on system needs.
OTG devices typically do not require a PC host, and can communicate directly with each other. For example, a PDA may act as a USB host with the capability to print directly to a USB printer, while also acting as a USB peripheral to communicate with a PC. In general, designers are facing increasing pressure to design smaller and faster products in less time and at lower cost. Concurrently, the introduction of smaller deep sub-micron processes present new challenges, such as integrating the physical layer (PHY—transceiver) analog circuitry required by technologies such as USB and OTG, leading to increased man-hours, fiscal and time investment, and silicon revisions. One way to increase time-to-market while keeping costs low is to provide the PHY in a separate chip. In such a case the designer can typically integrate most of the USB digital logic into the application specific integrated circuit (ASIC) in a small amount of time, and connect to a proven external PHY already available on the market.
Following the release of the USB 2.0 specification, Intel released the USB 2.0 Transceiver Macrocell Interface (UTMI) specification. UTMI defined an interface between two IP blocks, the USB Transceiver Macrocell (IP) and the USB Link layer (SIE). For example, the UTMI can be used to interface between a USB Link and a USB PHY. The signals for a UTMI interface with an 8-bit bi-directional data bus. Typically a minimum of 22 signals is required between the Link and the PHY for a device.
Subsequently, an extension of the original UTMI specification the UTMI+ specification was developed to meet the emerging need of building embedded host and OTG capabilities into USB devices. While the original UTMI specified an interface not meant to couple discrete ICs, the UTMI+ in essence introduced host and On-The-Go capabilities to USB systems. Using UTMI as a starting point, UTMI+ incrementally adds new functionality and interface signals to the Link and PHY. The additional signals total 33 for a full OTG UTMI+ interface. Designers can reuse all blocks from their original UTMI IP, and need only add the new circuits required for host or OTG support. This approach works well for UTMI+, as USB peripherals need only a subset of host and OTG functionality. UTMI+ introduced four levels of functionality, each higher level increasing the complexity required in both hardware and software while remaining completely backward compatible with lower levels.
A Low Pin Interface (LPI) UTMI+ specification, referred to as ULPI, was developed by USB industry leaders in order to provide low-cost USB and OTG PHYs by way of a low-pin, low-cost, small form-factor transceiver interface that may be used by any USB application. Pre-existing specifications, including UTMI and UTMI+ were developed primarily for Macrocell development, and were thus not optimized for use as an external PHY. Building upon the existing UTMI+ specification, the ULPI reduces the number of interface signals to 12 pins, with an optional implementation of 8 pins. As a result, the package size of PHY and Link IC's has generally been reduced, not only lowering the cost of Link and PHY IC's, but also reducing the required size of the associated printed circuit boards (PCBs). Central to the ULPI specification is the LPI, which is in effect a generic bus that defines a clock, three control signals, a bi-directional data bus, and bus arbitration. Typically, a ULPI link will configure the ULPI PHY using register writes on a bi-directional shared data bus. The ULPI PHY is the arbitrator of the 8-bit data bus between the link and the PHY.
Present day USB devices that may all communicate with a host computer system over USB include USB printers, scanners, digital cameras, storage devices, card readers, etc. USB based systems may require that a USB host controller be present in the host system, and that the operating system (OS) of the host system support USB and USB Mass Storage Class Devices. USB devices may communicate over the USB bus at low-speed (LS), full-speed (FS), or high-speed (HS). A connection between the USB device and the host may be established via digital interconnect such as Interchip USB, ULPI, UTMI, etc., (as described above) or via a four wire interface that includes a power line, a ground line, and a pair of data lines D+ and D−. When a USB device connects to the host, the USB device may first pull a D+ line high (the D− line if the device is a low speed device) using a pull up resistor on the D+ line. The host may respond by resetting the USB device. If the USB device is a high-speed USB device, the USB device may “chirp” by driving the D− line high during the reset. The host may respond to the “chirp” by alternately driving the D+ and D− lines high. The USB device may then electronically remove the pull up resistor and continue communicating at high speed. When disconnecting, full-speed devices may remove the pull up resistor from the D+ line (i.e., “tri-state” the line), while high-speed USB devices may tri-state both the D+ and D− lines.
A recent addition to the continuing development of the USB specification has been the USB 2.0 Link Power Management (LPM) Addendum, which is a new method to reduce the power demands of low bandwidth peripherals when connected to a portable device using the USB 2.0 specification. In general, the LPM ECN (Engineering Change Notice) adds a new power state (a power sleep state) between the existing enabled and suspended states. A USB Device in power sleep state is not required to reduce its power consumption. However, switching between the enabled state and sleep state is much faster than switching between the enabled state and suspended state, allowing devices to sleep while in idle mode. To reduce the configured current that the HOST is required to source on the USB Vbus connector, the LPM implements an Extended Transaction to suspend the peripheral faster than what would be possible under a standard USB 2.0 configuration.
The LPM Extended Transaction uses the he remaining USB 2.0 reserved PID (Physical Interface Device) value (4′b0), which is in the Special PID type group, to create a new Extension Token transaction (EXT PID). This EXT PID (“extended token 4′b0”) is not supported by ULPI PHYs, however, since the reserved PID value 4′b0 is used in the ULPI Chirp transaction. Hence, there is currently no PHY support for USB 2.0 LPM using the ULPI PHY interface standard. In other words, USB devices which have PHY and LINK portions that interface using ULPI cannot take advantage of the power saving features of the LPM Addendum, because the reserved PID value used for the LPM Extended Transaction is already used for other purposes in ULPI.
Other corresponding issues related to the prior art will become apparent to one skilled in the art after comparing such prior art with the present invention as described herein.